6I24-16

Manual

The MESA 6I24 is a low cost, general purpose, Xilinx XC6SLX16-2FTG256C FPGA based programmable I/O card for the PCIE bus. The 6I24 is a low profile one lane PCIE card (available with low profile and standard brackets, low profile bracket shown here)   Firmware modules are provided for hardware step generation, quadrature encoder counting,  PWM generation, digital I/O,  Smart Serial remote I/O, BISS, SSI, SPI, UART interfaces and more.  All motion control firmware is open source and easily modified to support new functions or different mixes of functions. All I/O bits are 5V tolerant and can sink 24 mA. All I/O pins support 3.3V LVDS signaling. Pullup resistors are provided for all pins so that they may be connected directly to opto-isolators, contacts etc.   The 6I24 has 72 I/O bits available on three 50 pin connectors, all connectors use I/O module rack compatible pinouts and are compatible with all Mesa 50 pin FPGA daughtercards.